STA

Preface 

                 Digital circuits run on clocks. Clock becomes heart beat of the circuit. We can predict the state of all the memory elements (flip flops) on a given clock cycle. To ensure determinism the data that is getting changed in the subsequent clock cycles need to adhere to few constraints. These constraints are nothing but setup and hold time requirements.

              This page can be used as an index for the STA related posts in this blog. Of course you can browse through the labels on the right to get the full view of the posts, this page would give u a birds overview of whats in store for STA concepts.

Index

• Types of timing analysis 
• Setup and hold time basics
• Delay Calculation Basics
• Process Corners... What and Why ?

             

Having known how the STA is beneficial in terms of run times and coverage let us now know on how this is used in the ASIC design cycle. Timing analysis is performed on different stages of the design cycle (broadly classified into three stages),

1. Synthesize
2. Place and Route
3. Sign-off checks