ASIC SYNTHESIS - PART 1 (INTRODUCTION)

                

             Synthesis is a process of converting higher abstraction level (HDL Coding) into lower abstraction level (Gate Netlist). This process is termed as synthesis because it is the process in which we combine the various basic gates into a full chip netlist as described in the HDL (Hardware Description Language). It also involves making the design adhere to the requirements like timing, area and power. Nowadays the size and complexity of the chips have increased multi-fold. Hence we cannot do it manually. Also the purpose of higher abstraction that HDL gives to designers is of no use if we have to do the synthesize manually. There are couple of tools available from the EDA companies which does a good job for us. 

  

                 In order for you to become an expert in synthesis you have to have first know three things,

• Overall flow - You need to understand the very existence of the synthesis in the IC design flow. Synthesis in itself involves many stages. you need to know what are they and why are they important. 
• Tool behavior - Tools help us a lot in automating the stuff. We have to know how we can best benefit from the tool available to us. A good command over the tool that we use saves us a lot of time in debug and helps us to achieve our goals sooner.                                                                     
• Hands On - Unless you practice all that you have learnt you will never become an expert. Without hands on you even forget the concepts and tool commands. You can easily develop an synthesis flow for yourself for practice.                            

               But am not going to cover the three things separately. What i will try to show is how a real time synthesis is done, what are the inputs, what are the outputs, what are the things we have to take care, Is the quality of the output met out requirements etc. Okay lets get started. Before you start any thing you have to make sure you have all the inputs that are required for the job. In Synthesis most of the quality that you get is based on the quality and completeness of the inputs.

               What i have decided is to code a simple design by hand in system verilog and explain every step until the scan netlist is generated with good quality. By following these series of posts you will be able to 

1. Understand basics of System Verilog for RTL coding.
2. Setup synthesis environment.
3. Perform power aware synthesis using Design Compiler Topo.
4. Know Scan techniques and flow.

                Assumption is you know 

     1. Basics of Verilog.

     2. Know where synthesis stands in the IC design flow.

     3. Know why scan is required.

     

Introduction to synthesis

                In the early days when the transistors are getting started to get integrated into a single chip, there was no RTL coding or the synthesis. In those days the number of transistors that are fabricated are very few and there fore all the layout of the chip is done manually. Also there was no tools available those days. As the technology develops the number of logic gates in the chip increased exponentially and people found it difficult and error prone do do such task manually. Therefore they invented RTL coding languages like verilog, vhdl etc. And tools to infer logic from those RTL discriptions. RTL coding gives coders the freedom to define the functionality of the chip without the dependency on the technology. Later those RTL codes will be feed into the synthesis tools that would parse the RTL descriptions and infers the hardware from them.

                 Synthesis is technology dependent. Synthesis literally means getting together two or many entities to form something new. Before going further you need to understand two methods of designing integrated circuits, semi custom and full custom. Full custom design methodology is one in which we would specify the layout of each transistor and interconnect. An alternative to it is semi custom in which standard sub circuits are built using transistors and used for building the full chip. Standard cell library usage is an example of semi custom methodology. Standard cells are intern developed by full custom methodology. Most of the design companies use semi custom design methodology. Very few companies like Intel use full custom methodology. Full custom methodology potentially increases performance and minimizes its area compared to semi custom design. But full custom is labor intensive and suitable only for very large scale production.
               Synthesis tools like Design compiler from Synopsys and RTL compiler from Cadence read in the RTL description along with the technology library which contains standard cells and macros for that technology and gives an output of circuit implementation only with the technology cells. One of the biggest task accomplished by the synthesis tool is the optimization. Before these tools all these optimizations are done manually using K-maps , drawing schematic etc. It takes into consideration design goals like timing , area and power into consideration while performing optimization.
               Synthesis at this stage is often  referred to as logic synthesis because we would only synthesize logic elements flops and computational logic but not clock network, reset network etc. They are done in the physical design stage during clock tree synthesis (CTS). In synthesis clocks are treated as ideal. It means we assume all the flops in the design get ideal clocks without any skew and zero transition. Clock latency is also taken as zero. We will discuss about these terms later in our discussions.
               
This is the best video to know an overview of synthesis :