ASIC SYNTHESIS - PART 1 (INTRODUCTION)

                

             Synthesis is a process of converting higher abstraction level (HDL Coding) into lower abstraction level (Gate Netlist). This process is termed as synthesis because it is the process in which we combine the various basic gates into a full chip netlist as described in the HDL (Hardware Description Language). It also involves making the design adhere to the requirements like timing, area and power. Nowadays the size and complexity of the chips have increased multi-fold. Hence we cannot do it manually. Also the purpose of higher abstraction that HDL gives to designers is of no use if we have to do the synthesize manually. There are couple of tools available from the EDA companies which does a good job for us. 

  

                 In order for you to become an expert in synthesis you have to have first know three things,

• Overall flow - You need to understand the very existence of the synthesis in the IC design flow. Synthesis in itself involves many stages. you need to know what are they and why are they important. 
• Tool behavior - Tools help us a lot in automating the stuff. We have to know how we can best benefit from the tool available to us. A good command over the tool that we use saves us a lot of time in debug and helps us to achieve our goals sooner.                                                                     
• Hands On - Unless you practice all that you have learnt you will never become an expert. Without hands on you even forget the concepts and tool commands. You can easily develop an synthesis flow for yourself for practice.                            

               But am not going to cover the three things separately. What i will try to show is how a real time synthesis is done, what are the inputs, what are the outputs, what are the things we have to take care, Is the quality of the output met out requirements etc. Okay lets get started. Before you start any thing you have to make sure you have all the inputs that are required for the job. In Synthesis most of the quality that you get is based on the quality and completeness of the inputs.

               What i have decided is to code a simple design by hand in system verilog and explain every step until the scan netlist is generated with good quality. By following these series of posts you will be able to 

1. Understand basics of System Verilog for RTL coding.
2. Setup synthesis environment.
3. Perform power aware synthesis using Design Compiler Topo.
4. Know Scan techniques and flow.

                Assumption is you know 

     1. Basics of Verilog.

     2. Know where synthesis stands in the IC design flow.

     3. Know why scan is required.