About DEF (Design Exchange Format)

Design Exchange Format (DEF) is an open specification for representing physical layout of an Integrated Circuit in an ASCII format. DEF file contains logical design data and Physical design data.
Logical design data includes

• Internal connectivity (as represented by netlist).                       
• Grouping information and
• Physical Constraints.

Physical design data includes

• Placement locations and orientations.
• Routing geometry data.
• Logical design data for back annotation.

It is not mandatory for a DEF file to have both logical and physical design data. In many cases the DEF netlist information is maintained in a separate file (usually in verilog) or in a separate DEF file. DEF file can be used only to pass placement information also.

The DEF file can contain following statements,

[ VERSION statement ]

[ DIVIDERCHAR statement ]

[ BUSBITCHARS statement ]

DESIGN statement

[ TECHNOLOGY statement ]

[ UNITS statement ]

[ HISTORY statement ] ...

[ PROPERTYDEFINITIONS section ]

[ DIEAREA statement ]

[ ROWS statement ] ...

[ TRACKS statement ] ...

[ GCELLGRID statement ] ...

[ VIAS statement ]

[ STYLES statement ]

[ NONDEFAULTRULES statement ]

[ REGIONS statement ]

[ COMPONENTS section ]

[ PINS section ]

[ PINPROPERTIES section ]

[ BLOCKAGES section ]

[ SLOTS section ]

[ FILLS section ]

[ SPECIALNETS section ]

[ NETS section ]

[ SCANCHAINS section ]

[ GROUPS section ]

[ BEGINEXT section ] ...

END DESIGN statement

Now let us know about what these statements implies,

BLOCKAGES:
                     Used to define placement and routing blockages. You can only associate blockages with placed instances. When the instance is moved, blockages also moves with it.

                Syntax :
                          [BLOCKAGES numBlockages ;
                                        [- LAYER layerName
                                             [+ COMPONENT compName | + SLOTS | + FILLS | + PUSHDOWN]
                                             [+ SPACING minSpacing | + DESIGNRULEWIDTH effectiveWidth]
                                                   {RECT pt pt | POLYGON pt pt pt ...} ...
                                        ;] ...
                                        [- PLACEMENT
                                        [+ COMPONENT compName | + PUSHDOWN]
                                                 {RECT pt pt} ...
                                        ;] ...
                          END BLOCKAGES]

                COMPONENT - Specifies the component with which the blockage needs to be associated.
                                             Usually placed instances can be used. It can be routing blockage or placement
                                             blockage.

PROCESS ANTENNA EFFECT (PAE)

Background :

                                 In a chip manufacturing process, metal layers are built up layer by layer starting with the first metal layer metal1. Then metal1 to metal2 via is created. Then metal3 is created and so on. In order to build the metal layer, the layer is first deposited with metal so that it covers the entire chip. Later the unwanted metal portions are removed usually using dry etching which allows good control of the shapes over the wet etching. This is done by using plasma etching process. Plasma contains charged particles that react with the solids to form volatile products which can be evaporated leaving behind only needed metal traces.

In the figure given above, Gx represents the Gate areas of the transistors, N(i,j) represents the metal segments. i represents the metal layer and j is a sequential number assigned to the metal segments. As i said already during the metallization process plasma etching process is used which involves charged particles, the metal segments collect charge from the plasma and develops a potential. Since the metal geometries develop charge during the metallization process they are called as the process antennas.

What is the problem with this process antennas ?

             Since the process antennas develop a voltage potential, they can exceed the threshold such a way that the voltage potential might cause current to pass across the gate oxide. This current that passes through the gate oxide might damage the gate oxide which causes the yield issues. This effect which is caused due to the process antennas on the gate oxide of the transistor is called as process antenna effect.

What is the Antenna ratio ?

              Because the total gate area the is electrically connected to a node (and therefore connected to the process antennas) determine the amount of charge from the process antennas the electrically connected gates can withstand, and because the size of the process antennas connected to the node determines how much charge the antennas collect, it is useful to calculate the ratio of the size of the process antenna on a node to the size of the gate area that is electrically connected to the node. This is the antenna ratio. The grater the antenna ratio, the grater the potential for damage to the gate oxide.
              If you are doing the antenna analysis on the chip and found that the antenna ratio is grater than the threshold specified by the foundry, gate damage is likely to occur.

The figure above shows the area of the process antennas and the area of the gate electrically connected to the node. The ratio between them is called antenna ratio.

What can be done to improve the Antenna Ratio ?

            One simple way is by providing an alternate path for the current that is supposed to pass through the gate oxide thereby damaging it. Such alternate path can be provided by using zener diode. By providing a path from the metal geometry to the substrate through the zener diode, the voltage potential that exceeds the threshold voltage that would damage the gate oxide can be configured as the breakdown voltage for the zener diode, which would then provides an alternate path for the current to pass through.
            The routing tools usually decreases the antenna ratio by tho methods,

•  By changing the routing by breaking the metal segments into smaller pieces. This would limit the charge collected by the metal segment that is exposed to the plasma. To do this the routing tool pushes the metal wire up or down one metal layer whenever it finds that the antenna ratio set in the LEF file is exceeded. The router changes the routing by disconnecting nets with antenna violations and making the connections to higher metal layers instead. It does not make the connections to lower layers. This method works because the top metal layer always completes the connection from the gate to the output drain area of the driver, which is a diode that provides a discharge path.

• By inserting antenna diode cells in the design,  the electrical charges on the metal that connects the diodes is then discharged through the diode diffusion layer and substrate. The routing tool inserts the diode cells automatically.

             

LEF (Library Exchange Format)

                LEF file contains library information for a class of designs. Library data includes layer, via, placement site type, and macro cell definitions. You can define all of your library information in a single LEF file. However this creates a large file that can be complex and hard to manage. Instead you can devide the information into two files,
               1.  "technology" LEF file
                2. "cell library" LEF file.

Technology LEF file :

              This file contains all of the LEF technology information for a design, such as placement and routing design rules, and process information for layers. It may contain following statements

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[UNITS statement]
[MANUFACTURINGGRID statement]
[USEMINSPACING statement]
[CLEARANCEMEASURE statement ;]
[PROPERTYDEFINITIONS statement]
[LAYER (Nonrouting) statement
| LAYER (Routing) statement] ...
[SPACING statement ]
[MAXVIASTACK statement]
[VIA statement] ...
[VIARULE statement] ...
[VIARULE GENERATE statement] ...
[NONDEFAULTRULE statement] ...
[SITE statement] ...
[BEGINEXT statement] ...
[END LIBRARY]

Cell Library LEF file :

                     This file includes the macro and standard cell information for a design. This file can include any of the following statements,

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[VIA statement] ...
[SITE statement]
[MACRO statement
[PIN statement] ...
[OBS statement ...] ] ...
[BEGINEXT statement] ...
[END LIBRARY]

Ok now let us understand in brief what the above statements are used for.

BUSBITCHARS :
                    Specifies pair of characters that can be used to specify the bus bits.
Example when you are going to use "[]" for specifying bus bit characters, like signal[8:0] then you need to define it before using it as,
                        BUSBITCHARS "[]" ;

CLEARANCEMEASURE :
                    Defines the clearance spacing requirement. This is nothing but the spacing between the objects.
This will be applied to pins and blockages in the cells. The two types that you can specify is,
                [CLEARANCEMEASURE {MAXXY | EUCLIDEAN} ;]

            MAXXY - Uses the largest of x or y for spacing between the objects.
            EUCLIDEAN -  Uses x2 + y2 distance for spacing.

DIVIDERCHAR :
                    Specifies the character used for hierarchy separation. Default value is "/"
                           DIVIDERCHAR "/" ;

BEGINEXT with ENDEXT: 
                   This commands can be used to add new custom syntax or just specify information other than what LEF file is intended for. The tools will ignore them if they are not supported by them. Example :

                       BEGINEXT "1VSI Signature 1.0"
                       CREATOR "company name"
                       DATE "timestamp"
                       REVISION "revision number"
                       ENDEXT

LAYER : 
                  This is the most important command since it almost defines 90 % of the LEF file information. The integrated circuit usually has many layers. The number of layers usually differs. The layers need to be defined in the process order from bottom to top as shown,

                  poly             masterslice
                  cut01           cut
                  metal1         routing
                  cut12           cut
                  metal2          routing
                  cut23           cut
                  metal3          routing
                  .....

You have to visualize the chip in a 3D view something like the picture bellow,

Can you see how the top metal layers are connected to the metal layers bellow ? Those connections are called via. The Cut layer is the one which has the vias. Now let us learn how each layer is defined in LEF file:

      1. LAYER (cut) :
                    Cut layer consist of the 'via' connecting the metal layer above to the layer bellow. There are many attributes that are used to specify the cut layer rules. Let us see them in brief.

          ACCURRENTDENSITY - Specifies how much AC current the cut layer of certain area can handle
                                                      at a certain frequency.
          ANTENNAAREAFACTOR - This is some thing like a derate factor. The metel layers should adhere
                                                        to the antenna rules of the technology. In order to calculate the metal
                                                        area the actual metal area is multiplied with this area factor. To know in
                                                        detail about the antenna effect see process antenna effect.
          ANTENNAAREARATIO - Specifies the ratio of metal area to the diffusion area connected to the
                                                       metal node.
          ANTENNACUMAREARATIO -