PROCESS ANTENNA EFFECT (PAE)

Background :

                                 In a chip manufacturing process, metal layers are built up layer by layer starting with the first metal layer metal1. Then metal1 to metal2 via is created. Then metal3 is created and so on. In order to build the metal layer, the layer is first deposited with metal so that it covers the entire chip. Later the unwanted metal portions are removed usually using dry etching which allows good control of the shapes over the wet etching. This is done by using plasma etching process. Plasma contains charged particles that react with the solids to form volatile products which can be evaporated leaving behind only needed metal traces.

In the figure given above, Gx represents the Gate areas of the transistors, N(i,j) represents the metal segments. i represents the metal layer and j is a sequential number assigned to the metal segments. As i said already during the metallization process plasma etching process is used which involves charged particles, the metal segments collect charge from the plasma and develops a potential. Since the metal geometries develop charge during the metallization process they are called as the process antennas.

What is the problem with this process antennas ?

             Since the process antennas develop a voltage potential, they can exceed the threshold such a way that the voltage potential might cause current to pass across the gate oxide. This current that passes through the gate oxide might damage the gate oxide which causes the yield issues. This effect which is caused due to the process antennas on the gate oxide of the transistor is called as process antenna effect.

What is the Antenna ratio ?

              Because the total gate area the is electrically connected to a node (and therefore connected to the process antennas) determine the amount of charge from the process antennas the electrically connected gates can withstand, and because the size of the process antennas connected to the node determines how much charge the antennas collect, it is useful to calculate the ratio of the size of the process antenna on a node to the size of the gate area that is electrically connected to the node. This is the antenna ratio. The grater the antenna ratio, the grater the potential for damage to the gate oxide.
              If you are doing the antenna analysis on the chip and found that the antenna ratio is grater than the threshold specified by the foundry, gate damage is likely to occur.

The figure above shows the area of the process antennas and the area of the gate electrically connected to the node. The ratio between them is called antenna ratio.

What can be done to improve the Antenna Ratio ?

            One simple way is by providing an alternate path for the current that is supposed to pass through the gate oxide thereby damaging it. Such alternate path can be provided by using zener diode. By providing a path from the metal geometry to the substrate through the zener diode, the voltage potential that exceeds the threshold voltage that would damage the gate oxide can be configured as the breakdown voltage for the zener diode, which would then provides an alternate path for the current to pass through.
            The routing tools usually decreases the antenna ratio by tho methods,

•  By changing the routing by breaking the metal segments into smaller pieces. This would limit the charge collected by the metal segment that is exposed to the plasma. To do this the routing tool pushes the metal wire up or down one metal layer whenever it finds that the antenna ratio set in the LEF file is exceeded. The router changes the routing by disconnecting nets with antenna violations and making the connections to higher metal layers instead. It does not make the connections to lower layers. This method works because the top metal layer always completes the connection from the gate to the output drain area of the driver, which is a diode that provides a discharge path.

• By inserting antenna diode cells in the design,  the electrical charges on the metal that connects the diodes is then discharged through the diode diffusion layer and substrate. The routing tool inserts the diode cells automatically.