In the early days when the transistors are getting started to get integrated into a single chip, there was no RTL coding or the synthesis. In those days the number of transistors that are fabricated are very few and there fore all the layout of the chip is done manually. Also there was no tools available those days. As the technology develops the number of logic gates in the chip increased exponentially and people found it difficult and error prone do do such task manually. Therefore they invented RTL coding languages like verilog, vhdl etc. And tools to infer logic from those RTL discriptions. RTL coding gives coders the freedom to define the functionality of the chip without the dependency on the technology. Later those RTL codes will be feed into the synthesis tools that would parse the RTL descriptions and infers the hardware from them.
Synthesis is technology dependent. Synthesis literally means getting together two or many entities to form something new. Before going further you need to understand two methods of designing integrated circuits, semi custom and full custom. Full custom design methodology is one in which we would specify the layout of each transistor and interconnect. An alternative to it is semi custom in which standard sub circuits are built using transistors and used for building the full chip. Standard cell library usage is an example of semi custom methodology. Standard cells are intern developed by full custom methodology. Most of the design companies use semi custom design methodology. Very few companies like Intel use full custom methodology. Full custom methodology potentially increases performance and minimizes its area compared to semi custom design. But full custom is labor intensive and suitable only for very large scale production.
Synthesis tools like Design compiler from Synopsys and RTL compiler from Cadence read in the RTL description along with the technology library which contains standard cells and macros for that technology and gives an output of circuit implementation only with the technology cells. One of the biggest task accomplished by the synthesis tool is the optimization. Before these tools all these optimizations are done manually using K-maps , drawing schematic etc. It takes into consideration design goals like timing , area and power into consideration while performing optimization.
Synthesis at this stage is often referred to as logic synthesis because we would only synthesize logic elements flops and computational logic but not clock network, reset network etc. They are done in the physical design stage during clock tree synthesis (CTS). In synthesis clocks are treated as ideal. It means we assume all the flops in the design get ideal clocks without any skew and zero transition. Clock latency is also taken as zero. We will discuss about these terms later in our discussions.
This is the best video to know an overview of synthesis :
Synthesis tools like Design compiler from Synopsys and RTL compiler from Cadence read in the RTL description along with the technology library which contains standard cells and macros for that technology and gives an output of circuit implementation only with the technology cells. One of the biggest task accomplished by the synthesis tool is the optimization. Before these tools all these optimizations are done manually using K-maps , drawing schematic etc. It takes into consideration design goals like timing , area and power into consideration while performing optimization.
Synthesis at this stage is often referred to as logic synthesis because we would only synthesize logic elements flops and computational logic but not clock network, reset network etc. They are done in the physical design stage during clock tree synthesis (CTS). In synthesis clocks are treated as ideal. It means we assume all the flops in the design get ideal clocks without any skew and zero transition. Clock latency is also taken as zero. We will discuss about these terms later in our discussions.
This is the best video to know an overview of synthesis :
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