Setup and Hold Basics

           Synchronous designs have become very popular because of their deterministic behavior. All the data need to satisfy MAX (Setup) and MIN (hold) delay constraints. All this is determined by the clock. Clock in a synchronous design can be thought of as a heart beat of the system. Figure bellow illustrates a simple data propagation between two memory stages.

                      In the above diagram, there are two D flip-flops having a combinational logic between them. Td is the delay due to the combinational logic. Lets mark the flops as A and B for our simplicity. The requirement of the synchronous design is that the clocks that are interacting should have a fixed phase and frequency relationship. Lets us assume that Ck1 and Ck2 is propagated from a common starting point to the two flops as shown above. The latency due to this clock propagation from the start point to the flop clock pin is called as Clock Latency. This can be simplified as shown in the figure bellow.

In the above diagram, Ck1 and Ck2 are the clock latency of Clk1 and Clk2 respectively. Clocks usually have start point from either one of the following, PLL outputs, Primary inputs, Clock divider logics etc. Taking, 

                                  Tper as clock period

                                  Td-slow as maximum combinational delay.

                                  Tsu- Setup time of the flip flop

                                  Thold - Hold time of the flip flop

                                  Td-fast - minimum combinational delay.

 we can arive at the equations of the setup and hold time requirements.

Setup Requirement :

The setup requirement says that the clock period of the clock must be always be greater than or equal to the sum of the data delay , setup time and difference in the clock latency of the two clocks.

Hold Requirement :

The hold requirement states that the minimum delay of the data should be always greater than or equal to the hold time requirement and the difference in the clock latency of the two clocks.

Why is these requirements ?
               These equations are what the implementation engineer and all the tools try to satisfy. But why is this  requirement exist. Ok lets jump into the internals of the flip flop. D flip flop is a master slave latch gated by clock.

Latches are very simple in operation. when the gate is on the output reflects the input. when the gate is closed the last value is latched. But why are they not used instead of flip flops ? Because this is not reliable because the input changes are