ABOUT PLL (Phase Locked Loop)

       The Phase locked loop is a closed loop frequency control system based on the difference between the input clock signal and feedback clock signal from the VCO (Voltage Controlled Oscillator). Generally the PLL contains following components 

                    1. Phase and Frequency difference detector.

                    2. Voltage Controlled Oscillator.

                    3. Feedback Counter

                    4. Pre-scale Counter

                    5. Post-scale Counter

Phase and Frequency difference detector :

This circuit detects if the feedback clock signal is lagging or leading the input clock signal and generates an 'up' or 'down' signal. This Up or Down signal is used by the charge pump and VCO to align the phase and increase of decrease the output clock frequency.

The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.

The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.

When the reference clock and the feedback clock phases are aligned then the PLL is considered to be locked.

A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.

The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).

In the form of equations:

where:

• F_REF = F_IN / N

• F_VCO = F_REF × M = F_IN × M/N

• F_OUT = F_VCO / C = (F_REF × M) / C = (F_IN × M) / (N × C)

• F_VCO = VCO frequency

• F_IN = input frequency

• F_REF = reference frequency

• F_OUT = output frequency

• M = counter (multiplier), part of the clock feedback path

• N = counter (divider), part of the input clock reference path

• C = post-scale counter (divider)