Delay Calculation Basics

                                  Delay calculation is the fundamental of the static timing analysis. A timing path has two end points called StartPoint and EndPoint. Between those two end points will be one or more stages. A stage consist of a driver cell, RC network at the output of the cell. The figure bellow shows a stage.
                                  Driver here is the basic logic gates which internally made of transistors. The RC network comes because of the metal connection between the stages. The above diagram is a very simple example of a stage. Normally it would be very complex. The complexity comes when we open up the driver underlying circuitry made of transistors and the RC network connected to it would be very complex. It would be cumbersome and time consuming if we have to calculate delays of stages with all those complexities. Of course that is what SPICE simulations perform. Spice simulations are more accurate that the STA done on tools like PrimeTime. In the tools like PrimeTime these driver circuity and the RC network is modeled into simple driver model and reduced RC network models. Because of this reduced modelling that those tools are faster in calculating the stage delays. There is a cost associated because of this modelling. The tools claim that there is less than 5% difference in the results.
                                       

               The driver model is intended to give the same response as that with the actual transistor level circuitry. Similarly the reduced order network model is a simplified model of the original RC network which would provide similar response. The receiver model would represent the input capacitance of pin. There are two types of modelling used for representing the driver and receivers nowadays. They are
                            1. NLDM (Non Linear Delay Model)
                            2. CCS (Composite Current Source)
Non Linear Delay Models :                NLDM models are the widely used models representing the response characteristics of cells in the libraries. It is very simple and less time consuming for the tools to obtain the response of the cells. This model uses two dimensional tables to represent the cell delay, output slew and other timing checks. In this method of modelling the driver cell is modeled to be a voltage source with resistance in series (Thevenin Model). The receiver is modeled to be a load capacitor.

                The cell delay is represented in a two dimensional table with input transition and output capacitance as the select factors. In an essence we can say that the cell delay depends on the input transition and output capacitance. But the cell delay table is provided for various combinations of the cell state, like which pin to which pin is the timing arc, the state of the other related pins, the type of transition rise or fall etc. Here is an example of the cell delay table for an inverter,
              pin (out) {
                   max_transition : 1.0;
                   timing () {
                     related_pin : "in";
                     timing_sense : negative_unate ;
                     cell_rise (table_4x4) {
                       index_1 ("0.2, 0.3, 0.5, 0.8")
                       index_2 ("0.20, 0.40, 0.80, 1.10")  
                       values (  "0.0534, 0.0787, 0.0987, 0.1546"
                                     "0.0965, 0.1764, 0.1974, 0.2084"
                                     "0.1964, 0.2154, 0.2584, 0.2765"
                                     "0.2576, 0.2987, 0.3765, 0.4567" ) ;
                       }
           In the above example the cell delay is given for the case if the transition is rise. Similarly for the sequential cells the timing checks like setup and hold requirements are also specified in the two  dimensional tables like the one above.
               One of the disadvantages of the NLDM is that it assumes the output load to be only capacitance. But in reality the interconnect consist of capacitance as well as resistance. The resistance factor becomes more pronounced in the lower geometries. However the NLDM overcomes this by calculating the effective capacitance (a single capacitance value to account for both resistance and capacitance effect). Not only that the network incorporates R effect but the input capacitance of the receiver becomes non liner due to miller effect. Miller effect accounts for the increase in the equivalent input capacitance of an inverting voltage amplifier due to amplification of the effect of the capacitance between the input and output terminals. NLDM could not model it.
Composite Current Source :    
                Unlike the pin capacitance for the receiver specified in NLDMs the CCS models allow the specification of receiver capacitance in the different portion of the transitioning waveform. As we know already the input capacitance of the receiver pin capacitance varies in different portions of the transitioning waveform, the CCS models would specify the input capacitance separately in the initial (or leading) portion and at the trailing portion of the input transitioning waveform. Not only that he driver model is modeled to be a composite current source rather than the voltage source as in the NLDM models. This would help in modelling the cell delay accurately due to the R effect on the interconnect.
       
 
                        You can notice the the input capacitance as C1 and C2 in the above diagram. C1 is for the leading portion and C2 is for the trailing portion. Here in CCS models we have the liberty of specifying the input capacitance at the pin level and at the arc level where as in the NLDM models we can only specify at the arc level.
                       
Now that we have calculated the cell delay and the output waveform at the cell output using either the NLDM or the CCS models, we need to calculate the net delay.
Interconnect Delay :
                      Net delay is calculated based on the R C values of the interconnect. In the prelayout if you are synthesizing the design using the wire load models then the RC values per unit length of the wire are obtained from the library and the topology is selected based on the corner. There are three tree typologies, 1. worst case tree. 2. Typical case tree and 3. Best case tree. Let us discuss about this later in detail. The worst corner implementation would select worst case tree. If you are synthesizing the design using the topographical technology as provided by the Design Compiler tool then the actual RC values are annotated from the technology files. The topology is the actual physical topology. Having known the RC values and the topology of the interconnect the net delay is calculated using the elmore delay models.
                      Elmore delay can be calculated on an RC network. The delay value is calculated as R times the C. The delay values are summed for each stages of R and C to obtain the complete interconnect delay.
                   Delay end of Stage 1 = R1 * C1
                   Delay at end of stage 2 = R1 * C1 + C2 * (R1+R2)
                   Total interconnect delay = ∑ (i=1,N) Ci   (∑(j=1,i) Rj))
Okay. We have just seen how cell delay and net delay are calculated. A timing path delay is calculated based on the above mentioned ways and math is applied based on the clock period available and result thus tells whether the path is met or violated. Its that simple :-)