Process Corners... What and Why ?

                    Semiconductor manufacturing is very complex process with many stages. The complexity lies in the geometries that we are building chips. Technology is developing at a faster phase because of the market competition and demand. The transition from 90nm to 28nm happened within a decade. Wafer size grown from 200mm to 450mm. As the foundry vendors try to move on to the smaller geometries, the design companies need to verify the chip design thoroughly for all possible variability in the manufacturing process. Variability plays a major role in determining how best is the foundry manufacturing process.
                 The ideal goal is to produce every chip exactly the same. But it is not possible since not all the factors can be controlled to be in an ideal way. The conditions in which the chips are fabricated causes these variations in the properties. The heart of the foundry is the clean room. The temperature, humidity and even the vibrations are to be controlled.

                 Some of the process parameters like implant dose, channel length, threshold voltage can vary in some degrees. Hence the behavior of the transistors vary accordingly. What manufactures do is they make corner lots. Corner lots means they bundle the wafers based on these process parameters worst, typical and best. The characterization team couple temperature, voltage and frequency of operation with these process parameters and plot the responses on a plot called shmoo plot. Bellow picture shows the shmoo plot for a variable voltage. X in the bellow picture indicate positive response and "." a negative one.

                     Based on these plots we come to know the boundary beyond which the device will fail for the various combinations of these parameters. Actually these process variations arise due to many reasons such as the temperature and humidity in which the wafers are made, the precision of the manufacturing machines in which it can fabricate the dies. After the characterization is done, normally the characteristic responses of the devices are modeled  as NLDM or CCS libraries for worst typical and best conditions of the devices. They are normally named using a two letter terminology like SS, TT and FF etc. They mean fast, slow and typical carrier mobilities of the devices. Wonder why there are two characters ? First one is for NMOS and second is for PMOS. TT does not actually represent any relative process corner effect but its just the nominal corner over which the process technology would have most probable outcome. So we always want to test our devices in the extreme process variations to ensure that there is always a good margin for a better yield. Therefore the combination of process corners would be SS, FF, TT, SF and FS. SS, TT and FF corners are the even corners where we can expect strong correlation in the PMOS and NMOS behavior since both would be either slow or faster. But SF and FS corners are called as Skewed corners in which the delay exhibited by the PMOS and NMOS are different leading to output signal to have different slews on rise and fall edges. PMOS controls the rise transitions and NMOS controls the fall transitions of the output signal. If we have both of them operating at the same way the output transitions rise or fall would have same slew. But if they are different the transition will be different. We usually do not consider SF and FS corners because they get covered in the SS and FF corner.

                      SS - Slow NMOS and Slow PMOS
                      SF - Slow NMOS and Fast PMOS
                      FS - Fast NMOS and Slow PMOS
                      TT - Typical NMOS and Typical PMOS
                      FF - Fast NMOS and Fast PMOS

                     Now that we have understood the differences due to the process variations, the device characteristics also varies due to the voltage and temperature. We need to couple the voltage and temperature with the process corners to obtain the actual possible corners. Before that we have to understand the device characteristics for various voltages and temperature.
                            Semiconductor devices operate better with better voltage. Hence delay decreases with increase in the voltage. For a slow corner we would choose min voltage and for a fast corner we would choose max voltage. These min and max voltages are based on the voltage specifications of the product.

                       Max Voltage -> Less Delay
                       Min Voltage -> More Delay

                               When it comes to temperature, we need to be little cautious. In the technologies above 90nm delay increases as temperature increases. This is due to the fact that as the temperature increases the electrons collides more often that disrupts the stream line flow which makes the current flow. This effect is called lattice scattering. The lattice vibrations due to high temperature scatters the electrons. As the geometries scales smaller and smaller the effect of temperature on delay varies at lower temperature. At lower temperature the impurity scattering becomes dominant where as the thermal motion of the electron is slower. As the electrons moves slower they get easily scattered by the impurity ions. This effect becomes more dominant at lower voltages. Hence before we could decide on the corner for implementations and sign off we need to do a temperature inversion analysis.

What is temperature inversion analysis ?

              As we have seen that the delay of the cells cannot be scaled with the temperature we need to do a temperature inversion analysis to first understand the corners for which the cells in the library has more delay. This is very important since we may choose a single worst corner for implementation to avoid run times issues due to multi corner synthesize. The method to do this temperature inversion analysis is,

1. Select one cell for each type from the library. For example, and, or, exor, clock buffer, flop etc
2. Load the spice model of the cell into a spice simulation tool.
3. Note the delay of the cell using 50% to 50% transition from input to output and transition using 30% to 70% for various combination of input slew and load. 
4. Repeat step 3 and 4 for min temperature and max temperature using SS process corner and min voltage.
5. Form a two dimensional table for each cell type with slew and load in X and Y axis. Make such table for min and max temperature.
6. From the tables high light the max delay values. 

By analyzing the max delay values from each table we can identify the process, voltage and temperature (min/max) combination which produces the max cell delays. From that we can choose the worst corner for implementation. In case if the cell delay is more only for a few combinations of input slew and load, then we may have to choose temperature showing max delay for implementation and do a signoff check in both min and max temperature. This is called Partial temperature inversion. If you notice cell delays are maximum in all tables for min temperature, then we can safely avoid max temperature corner. One common trend is the temperature inversion becomes more dominant at min voltages. So if you are choosing min temperature then most probable there should be min voltage along with that.         
                    

             Similar to the different corners that exist to the PMOS and NMOS, there are different corners for interconnect as well.

Interconnect Corners :

              Interconnects also experience some variations due to the manufacturing process technology. The width, thickness of the metal traces, dielectric constant of the spacing and width of the spacing can vary. Because of this the resistance and capacitance of the metal traces vary which ultimately has an impact on the delay of the interconnect. See the picture bellow to better understand the interconnect process variation effects on the delay. 

       The picture above is how the metal traces appear when you cut the chip into two pieces and look into the cut portion. Adjacent metal layers are oriented at 90 degree angles. Between the metal traces is the dielectric material (like Si02). Because of the variation in the height and width of the metal traces the capacitance and resistance varies. 

1. Resistance increases if  

• Width decreases.
• Temperature increases.

2. Capacitance increases if 

• Spacing between the metal traces decreases.
• Height increases.

As the technology nodes gets smaller and smaller the above mentioned factors fuels increase in resistance and capacitance. As we know delay is calculated for an interconnect by the formula,

                                  Delay = R*C

Today there are 5 corners that are being used for interconnects. They are,

• C Best : In this the Capacitance of the interconnect is minimum. Capacitance becomes minimum when there is minimum Height, Width of the metal trace, hence resistance increases. 

• C Worst : In this the Capacitance of the interconnect is maximum. Capacitance becomes maximum when there is maximum Height, Width of the metal trace hence resistance decreases.

• RC Best : In this the product of the RC is minimum, in other words the interconnect delay is minimum. We cannot exactly predict the R/C contributions for the delay.

• RC Worst : In this the product of the RC is maximum, in other words the interconnect delay is maximum. We cannot exactly predict the R/C contributions for the delay.

• Typical : This is the corner in which the interconnects are fabricated mostly. The delay is typical.

While selecting the corners for the timing analysis, temperature needs to be considered. At low temperature the metal exhibits low resistance but ah high temperature  its quite opposite. Hence if you analyze the timing of a net at min and max temperature, it will differ a lot.  Hence we need to do an analysis of the net delays based on the above mentioned corners and parameters on our technology library to know what combinations gives worst / best delays.