Verilog is a great language which is widely used in Industry but it had few limitations. Verilog is not helping verification engineers much. Also there were few ambiguities in designer code. Also the code is not precise. To over come these limitations verilog was enhanced to System verilog. SV is verification frendly which supports object oriented programming. It eliminated synthesis simulation misinterpretations and also made the code precise and easily maintainable. The objective of this post is to show the basic things which a designer need to know to code a design in SV.
First thing which differs SV from verilog is the enhanced data types. In hardware description language there is no such thing called data types. Hardware signal can be
logic 1,
logic 0,
Unknown (X) and
high impedance (Z).
In verilog the register and wire were used for the storing and connecting two storage units (flip flop). In system verilog the following data types can be used for RTL coding.
- Logic - 4 stage variable and user defined size (can be used instead of reg and wire )
- Enum - Variable which can have only user defined values
- int - 32 bit , 2 stage integer variable. (can be used instead of integer)
Enum is very useful variable which can store user defined data types. It helps especially while coding the state machines.
Example :
enum logic [2:0]
{ START = 3'b100,
PROCESS = 3'b010,
STOP = 3'b001}
state, next_state ;
enum logic [2:0]
{ START = 3'b100,
PROCESS = 3'b010,
STOP = 3'b100}
state, next_state ;
But a traditional verilog code using the parameter would not show any compiler issues since the values assigned are for different variables.
parameter
START = 3'b100,
PROCESS = 3'b010,
STOP = 3'b100;
struct :
Another very useful enhancement that system verilog brings is the structures. In RTL coding the structures can be used to bundle related signals together.
struct {
logic Enable1;
logic [9:0] Data1;
logic Ack1;
} bus1;
We can assign values to the entire structure in a single assignment which reduces the number of lines in the rtl code.
bus1 = `{1'b1, 10'b0101010101, 1'b1};
This is how we assign value to a member of struct.
bus1.Ack1 = 1'b0 ;
typedef :
SV also supports user defined data types using typedef. It can be used to define some complex data types which user might need to use multiple times easily. We need to know that we are creating a new data type using the typedef not the variable itself.
typedef logic [63:0] bus_64 ;
you could use the data type bus_64 that we created using typedef to create new variables of that kind.
bus_64 output; (Here we have declared output as a 64 bit bus using typedef bus_64 which is created earlier)
packages :
Often we might require to define the same variables or fuctions in multiple files which is duplication of same piece of code. SV has introduced packages that we could use it to simplify the re declaration and maintain consistency in the code.
package common_def {
typedef logic [31:0] bus_64;
enum logic [2:0]
{ START = 3'b100,
PROCESS = 3'b010,
STOP = 3'b001
} state, next_state ;
struct {
logic Enable1;
logic [9:0] Data1;
logic Ack1;
} bus1;
endpackage
The package common_def can be imported to any system verilog file using import command and there you get all the definitions.
import common_def::*;
module control ();
bus_64 system_bus;
...
endmodule
array :
SV also supports multi dimensional arrays which are synthesize-able. The advantages is we could address the whole bunch of bits together in one assignment.
logic [31:0] data ; (Normal verilog 32 bit variable)
logic [1:0] [3:0] [3:0] data ; (Multi dimentional 32 bit variable)
The advantage is we could assign values in different ways,
assign data [1][1][1] = 1'b1;
assign data [1][1] = 4'hF;
Lets discuss about interfaces , procedural blocks and other enhancements in next part.
