Delay Calculation Basics

                                  Delay calculation is the fundamental of the static timing analysis. A timing path has two end points called StartPoint and EndPoint. Between those two end points will be one or more stages. A stage consist of a driver cell, RC network at the output of the cell. The figure bellow shows a stage.
                                  Driver here is the basic logic gates which internally made of transistors. The RC network comes because of the metal connection between the stages. The above diagram is a very simple example of a stage. Normally it would be very complex. The complexity comes when we open up the driver underlying circuitry made of transistors and the RC network connected to it would be very complex. It would be cumbersome and time consuming if we have to calculate delays of stages with all those complexities. Of course that is what SPICE simulations perform. Spice simulations are more accurate that the STA done on tools like PrimeTime. In the tools like PrimeTime these driver circuity and the RC network is modeled into simple driver model and reduced RC network models. Because of this reduced modelling that those tools are faster in calculating the stage delays. There is a cost associated because of this modelling. The tools claim that there is less than 5% difference in the results.
                                       

               The driver model is intended to give the same response as that with the actual transistor level circuitry. Similarly the reduced order network model is a simplified model of the original RC network which would provide similar response. The receiver model would represent the input capacitance of pin. There are two types of modelling used for representing the driver and receivers nowadays. They are
                            1. NLDM (Non Linear Delay Model)
                            2. CCS (Composite Current Source)
Non Linear Delay Models :                NLDM models are the widely used models representing the response characteristics of cells in the libraries. It is very simple and less time consuming for the tools to obtain the response of the cells. This model uses two dimensional tables to represent the cell delay, output slew and other timing checks. In this method of modelling the driver cell is modeled to be a voltage source with resistance in series (Thevenin Model). The receiver is modeled to be a load capacitor.

                The cell delay is represented in a two dimensional table with input transition and output capacitance as the select factors. In an essence we can say that the cell delay depends on the input transition and output capacitance. But the cell delay table is provided for various combinations of the cell state, like which pin to which pin is the timing arc, the state of the other related pins, the type of transition rise or fall etc. Here is an example of the cell delay table for an inverter,
              pin (out) {
                   max_transition : 1.0;
                   timing () {
                     related_pin : "in";
                     timing_sense : negative_unate ;
                     cell_rise (table_4x4) {
                       index_1 ("0.2, 0.3, 0.5, 0.8")
                       index_2 ("0.20, 0.40, 0.80, 1.10")  
                       values (  "0.0534, 0.0787, 0.0987, 0.1546"
                                     "0.0965, 0.1764, 0.1974, 0.2084"
                                     "0.1964, 0.2154, 0.2584, 0.2765"
                                     "0.2576, 0.2987, 0.3765, 0.4567" ) ;
                       }
           In the above example the cell delay is given for the case if the transition is rise. Similarly for the sequential cells the timing checks like setup and hold requirements are also specified in the two  dimensional tables like the one above.
               One of the disadvantages of the NLDM is that it assumes the output load to be only capacitance. But in reality the interconnect consist of capacitance as well as resistance. The resistance factor becomes more pronounced in the lower geometries. However the NLDM overcomes this by calculating the effective capacitance (a single capacitance value to account for both resistance and capacitance effect). Not only that the network incorporates R effect but the input capacitance of the receiver becomes non liner due to miller effect. Miller effect accounts for the increase in the equivalent input capacitance of an inverting voltage amplifier due to amplification of the effect of the capacitance between the input and output terminals. NLDM could not model it.
Composite Current Source :    
                Unlike the pin capacitance for the receiver specified in NLDMs the CCS models allow the specification of receiver capacitance in the different portion of the transitioning waveform. As we know already the input capacitance of the receiver pin capacitance varies in different portions of the transitioning waveform, the CCS models would specify the input capacitance separately in the initial (or leading) portion and at the trailing portion of the input transitioning waveform. Not only that he driver model is modeled to be a composite current source rather than the voltage source as in the NLDM models. This would help in modelling the cell delay accurately due to the R effect on the interconnect.
       
 
                        You can notice the the input capacitance as C1 and C2 in the above diagram. C1 is for the leading portion and C2 is for the trailing portion. Here in CCS models we have the liberty of specifying the input capacitance at the pin level and at the arc level where as in the NLDM models we can only specify at the arc level.
                       
Now that we have calculated the cell delay and the output waveform at the cell output using either the NLDM or the CCS models, we need to calculate the net delay.
Interconnect Delay :
                      Net delay is calculated based on the R C values of the interconnect. In the prelayout if you are synthesizing the design using the wire load models then the RC values per unit length of the wire are obtained from the library and the topology is selected based on the corner. There are three tree typologies, 1. worst case tree. 2. Typical case tree and 3. Best case tree. Let us discuss about this later in detail. The worst corner implementation would select worst case tree. If you are synthesizing the design using the topographical technology as provided by the Design Compiler tool then the actual RC values are annotated from the technology files. The topology is the actual physical topology. Having known the RC values and the topology of the interconnect the net delay is calculated using the elmore delay models.
                      Elmore delay can be calculated on an RC network. The delay value is calculated as R times the C. The delay values are summed for each stages of R and C to obtain the complete interconnect delay.
                   Delay end of Stage 1 = R1 * C1
                   Delay at end of stage 2 = R1 * C1 + C2 * (R1+R2)
                   Total interconnect delay = ∑ (i=1,N) Ci   (∑(j=1,i) Rj))
Okay. We have just seen how cell delay and net delay are calculated. A timing path delay is calculated based on the above mentioned ways and math is applied based on the clock period available and result thus tells whether the path is met or violated. Its that simple :-)   

Assign output of the command to a variable in Shell Script

      We come across various situations where we need to dump the output of the analysis into an excel sheet to publish the result of analysis. In one of the situations i needed to make an csv format of the output analysis. This requires the computed values to be presented in a row for each entity.
       We know that our script works sequentially line by line. If you want to print a value in the current line u need to calculate it before to do so. But we can actually have multiple commands embedded in one line. The sub commands would execute first and later the parent command.

Example :

If you need the output file to have count based on the various grep patterns in one line you can do so like this,

set count1 = `grep "pattern1" filename | wc`
set count2 = `grep "pattern2" filename | wc`
set count3 = `grep "pattern3" filename | wc`
set count4 = `grep "pattern4" filename | wc`

echo "The counts are : $count1 , $count2 , $count3 , $count4" > outputfile

`-  back tick is used here. This can be used for executing a command inside another command. 

Introduction to synthesis

                In the early days when the transistors are getting started to get integrated into a single chip, there was no RTL coding or the synthesis. In those days the number of transistors that are fabricated are very few and there fore all the layout of the chip is done manually. Also there was no tools available those days. As the technology develops the number of logic gates in the chip increased exponentially and people found it difficult and error prone do do such task manually. Therefore they invented RTL coding languages like verilog, vhdl etc. And tools to infer logic from those RTL discriptions. RTL coding gives coders the freedom to define the functionality of the chip without the dependency on the technology. Later those RTL codes will be feed into the synthesis tools that would parse the RTL descriptions and infers the hardware from them.

                 Synthesis is technology dependent. Synthesis literally means getting together two or many entities to form something new. Before going further you need to understand two methods of designing integrated circuits, semi custom and full custom. Full custom design methodology is one in which we would specify the layout of each transistor and interconnect. An alternative to it is semi custom in which standard sub circuits are built using transistors and used for building the full chip. Standard cell library usage is an example of semi custom methodology. Standard cells are intern developed by full custom methodology. Most of the design companies use semi custom design methodology. Very few companies like Intel use full custom methodology. Full custom methodology potentially increases performance and minimizes its area compared to semi custom design. But full custom is labor intensive and suitable only for very large scale production.
               Synthesis tools like Design compiler from Synopsys and RTL compiler from Cadence read in the RTL description along with the technology library which contains standard cells and macros for that technology and gives an output of circuit implementation only with the technology cells. One of the biggest task accomplished by the synthesis tool is the optimization. Before these tools all these optimizations are done manually using K-maps , drawing schematic etc. It takes into consideration design goals like timing , area and power into consideration while performing optimization.
               Synthesis at this stage is often  referred to as logic synthesis because we would only synthesize logic elements flops and computational logic but not clock network, reset network etc. They are done in the physical design stage during clock tree synthesis (CTS). In synthesis clocks are treated as ideal. It means we assume all the flops in the design get ideal clocks without any skew and zero transition. Clock latency is also taken as zero. We will discuss about these terms later in our discussions.
               
This is the best video to know an overview of synthesis :

                          

  

Types of Timing Analysis

 We can perform timing closure on a digital circuit by two ways,

• Dynamic simulation
• Static timing analysis.

Dynamic simulations : 

                This is similar to the functional verification but the delay values of the circuit elements are considered. This is not exhaustive since it depends on the test vectors. Test vectors cannot stimulate all the possible paths. It is very time consuming to simulate the whole circuit for timing analysis. One of the advantages of dynamic timing analysis over the static timing analysis is that it is well suited for asynchronous interface timing. Static timing analysis cannot handle asynchronous timings.
                          Dynamic timing analysis can be run using the tools like Modelsim from Mentor graphics and VCS from synopsys.

Static timing analysis : 

                This method does not require test vectors. It does not check the functionality of the circuit. It can only check the timing of the circuit. All possible paths are taken into consideration and each path is analyzed in its worst possible scenario. It is very very fast compared to dynamic simulation. Because of this advantages it became the widely used method of timing closure in the IC designs. However dynamic simulation is also performed but just for sanity purpose and also only very few test cases are run (Gate Level Simulation).
                  The most popular tool used for timing analysis is Primetime from Synopsys.

Need for DFT

                     Functional verification will ensure that our circuit will work for all possible combinations of inputs. But what guarantee whether our manufacturing vendor has done his job perfectly ? DFT can help in this regard. We build test logic into our chip so that we can test the functional logic blocks for any design manufacturing defects. Our test logic should ensure 100% coverage so that we can say 100% that the chip is free from any manufacturing defects.

                     As the technology scales down, the smaller geometries are becoming difficult to realize and therefore the number of manufacturing defects are rising. DFT becomes an important technique to ensure all our shipments are defect free. Without the DFT test, no customer will be willing to buy our chip because when he uses the defected chip in his product he will loose the customer loyalty and good name.

                     Some of the manufacturing defects that we might expect are,

• Nodes may get shorted to power or ground.
• Dust particles can cause disconnections in the electrical paths.
• Short circuits may happen between source and drain of transistors.

Improving Tester Time :

         DFT is not just about providing the possibility of testing the chip for the manufacturing defects but also developing the test vectors that would otherwise save valuable tester time. Every chip out of the fab needs to be tested for manufacturing defects. Tester is a equipment facility that would do the testing of the chip. The time taken for the tester to test a chip is very important factor in the cost of the chip. Because tester times is very costly. The tester is usually referred to as Automatic test Equipment(ATE). These ATEs also log the test diagnostics that would help in identifying the source of the fault thereby preventing it in the manufacturing process itself.

                   
Yield improvements :

         DFT is tightly coupled with the yield of the technology used for manufacturing. Yield is the number of defect free chips in the total chips manufactured. During the ramp of next technology nodes there might be situation when there is zero yield. During that time DFT diagnostics play an very important role in identifying the failure points. 

           

Functional Debug :

          DFT infrastructure that is built into the chip can also be used for functional debug. For example if the chip is executing an assembly code and stuck at the some point, the functional clock can be stoped and chip can be put to test mode and all the state values of the important registers can be shifted out for debugging. Without DFT infra it would be otherwise very difficult to debug functional failures on silicon.

Here is one video lecture regarding DFT overview :

                              

About DEF (Design Exchange Format)

Design Exchange Format (DEF) is an open specification for representing physical layout of an Integrated Circuit in an ASCII format. DEF file contains logical design data and Physical design data.
Logical design data includes

• Internal connectivity (as represented by netlist).                       
• Grouping information and
• Physical Constraints.

Physical design data includes

• Placement locations and orientations.
• Routing geometry data.
• Logical design data for back annotation.

It is not mandatory for a DEF file to have both logical and physical design data. In many cases the DEF netlist information is maintained in a separate file (usually in verilog) or in a separate DEF file. DEF file can be used only to pass placement information also.

The DEF file can contain following statements,

[ VERSION statement ]

[ DIVIDERCHAR statement ]

[ BUSBITCHARS statement ]

DESIGN statement

[ TECHNOLOGY statement ]

[ UNITS statement ]

[ HISTORY statement ] ...

[ PROPERTYDEFINITIONS section ]

[ DIEAREA statement ]

[ ROWS statement ] ...

[ TRACKS statement ] ...

[ GCELLGRID statement ] ...

[ VIAS statement ]

[ STYLES statement ]

[ NONDEFAULTRULES statement ]

[ REGIONS statement ]

[ COMPONENTS section ]

[ PINS section ]

[ PINPROPERTIES section ]

[ BLOCKAGES section ]

[ SLOTS section ]

[ FILLS section ]

[ SPECIALNETS section ]

[ NETS section ]

[ SCANCHAINS section ]

[ GROUPS section ]

[ BEGINEXT section ] ...

END DESIGN statement

Now let us know about what these statements implies,

BLOCKAGES:
                     Used to define placement and routing blockages. You can only associate blockages with placed instances. When the instance is moved, blockages also moves with it.

                Syntax :
                          [BLOCKAGES numBlockages ;
                                        [- LAYER layerName
                                             [+ COMPONENT compName | + SLOTS | + FILLS | + PUSHDOWN]
                                             [+ SPACING minSpacing | + DESIGNRULEWIDTH effectiveWidth]
                                                   {RECT pt pt | POLYGON pt pt pt ...} ...
                                        ;] ...
                                        [- PLACEMENT
                                        [+ COMPONENT compName | + PUSHDOWN]
                                                 {RECT pt pt} ...
                                        ;] ...
                          END BLOCKAGES]

                COMPONENT - Specifies the component with which the blockage needs to be associated.
                                             Usually placed instances can be used. It can be routing blockage or placement
                                             blockage.

PROCESS ANTENNA EFFECT (PAE)

Background :

                                 In a chip manufacturing process, metal layers are built up layer by layer starting with the first metal layer metal1. Then metal1 to metal2 via is created. Then metal3 is created and so on. In order to build the metal layer, the layer is first deposited with metal so that it covers the entire chip. Later the unwanted metal portions are removed usually using dry etching which allows good control of the shapes over the wet etching. This is done by using plasma etching process. Plasma contains charged particles that react with the solids to form volatile products which can be evaporated leaving behind only needed metal traces.

In the figure given above, Gx represents the Gate areas of the transistors, N(i,j) represents the metal segments. i represents the metal layer and j is a sequential number assigned to the metal segments. As i said already during the metallization process plasma etching process is used which involves charged particles, the metal segments collect charge from the plasma and develops a potential. Since the metal geometries develop charge during the metallization process they are called as the process antennas.

What is the problem with this process antennas ?

             Since the process antennas develop a voltage potential, they can exceed the threshold such a way that the voltage potential might cause current to pass across the gate oxide. This current that passes through the gate oxide might damage the gate oxide which causes the yield issues. This effect which is caused due to the process antennas on the gate oxide of the transistor is called as process antenna effect.

What is the Antenna ratio ?

              Because the total gate area the is electrically connected to a node (and therefore connected to the process antennas) determine the amount of charge from the process antennas the electrically connected gates can withstand, and because the size of the process antennas connected to the node determines how much charge the antennas collect, it is useful to calculate the ratio of the size of the process antenna on a node to the size of the gate area that is electrically connected to the node. This is the antenna ratio. The grater the antenna ratio, the grater the potential for damage to the gate oxide.
              If you are doing the antenna analysis on the chip and found that the antenna ratio is grater than the threshold specified by the foundry, gate damage is likely to occur.

The figure above shows the area of the process antennas and the area of the gate electrically connected to the node. The ratio between them is called antenna ratio.

What can be done to improve the Antenna Ratio ?

            One simple way is by providing an alternate path for the current that is supposed to pass through the gate oxide thereby damaging it. Such alternate path can be provided by using zener diode. By providing a path from the metal geometry to the substrate through the zener diode, the voltage potential that exceeds the threshold voltage that would damage the gate oxide can be configured as the breakdown voltage for the zener diode, which would then provides an alternate path for the current to pass through.
            The routing tools usually decreases the antenna ratio by tho methods,

•  By changing the routing by breaking the metal segments into smaller pieces. This would limit the charge collected by the metal segment that is exposed to the plasma. To do this the routing tool pushes the metal wire up or down one metal layer whenever it finds that the antenna ratio set in the LEF file is exceeded. The router changes the routing by disconnecting nets with antenna violations and making the connections to higher metal layers instead. It does not make the connections to lower layers. This method works because the top metal layer always completes the connection from the gate to the output drain area of the driver, which is a diode that provides a discharge path.

• By inserting antenna diode cells in the design,  the electrical charges on the metal that connects the diodes is then discharged through the diode diffusion layer and substrate. The routing tool inserts the diode cells automatically.

             

LEF (Library Exchange Format)

                LEF file contains library information for a class of designs. Library data includes layer, via, placement site type, and macro cell definitions. You can define all of your library information in a single LEF file. However this creates a large file that can be complex and hard to manage. Instead you can devide the information into two files,
               1.  "technology" LEF file
                2. "cell library" LEF file.

Technology LEF file :

              This file contains all of the LEF technology information for a design, such as placement and routing design rules, and process information for layers. It may contain following statements

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[UNITS statement]
[MANUFACTURINGGRID statement]
[USEMINSPACING statement]
[CLEARANCEMEASURE statement ;]
[PROPERTYDEFINITIONS statement]
[LAYER (Nonrouting) statement
| LAYER (Routing) statement] ...
[SPACING statement ]
[MAXVIASTACK statement]
[VIA statement] ...
[VIARULE statement] ...
[VIARULE GENERATE statement] ...
[NONDEFAULTRULE statement] ...
[SITE statement] ...
[BEGINEXT statement] ...
[END LIBRARY]

Cell Library LEF file :

                     This file includes the macro and standard cell information for a design. This file can include any of the following statements,

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[VIA statement] ...
[SITE statement]
[MACRO statement
[PIN statement] ...
[OBS statement ...] ] ...
[BEGINEXT statement] ...
[END LIBRARY]

Ok now let us understand in brief what the above statements are used for.

BUSBITCHARS :
                    Specifies pair of characters that can be used to specify the bus bits.
Example when you are going to use "[]" for specifying bus bit characters, like signal[8:0] then you need to define it before using it as,
                        BUSBITCHARS "[]" ;

CLEARANCEMEASURE :
                    Defines the clearance spacing requirement. This is nothing but the spacing between the objects.
This will be applied to pins and blockages in the cells. The two types that you can specify is,
                [CLEARANCEMEASURE {MAXXY | EUCLIDEAN} ;]

            MAXXY - Uses the largest of x or y for spacing between the objects.
            EUCLIDEAN -  Uses x2 + y2 distance for spacing.

DIVIDERCHAR :
                    Specifies the character used for hierarchy separation. Default value is "/"
                           DIVIDERCHAR "/" ;

BEGINEXT with ENDEXT: 
                   This commands can be used to add new custom syntax or just specify information other than what LEF file is intended for. The tools will ignore them if they are not supported by them. Example :

                       BEGINEXT "1VSI Signature 1.0"
                       CREATOR "company name"
                       DATE "timestamp"
                       REVISION "revision number"
                       ENDEXT

LAYER : 
                  This is the most important command since it almost defines 90 % of the LEF file information. The integrated circuit usually has many layers. The number of layers usually differs. The layers need to be defined in the process order from bottom to top as shown,

                  poly             masterslice
                  cut01           cut
                  metal1         routing
                  cut12           cut
                  metal2          routing
                  cut23           cut
                  metal3          routing
                  .....

You have to visualize the chip in a 3D view something like the picture bellow,

Can you see how the top metal layers are connected to the metal layers bellow ? Those connections are called via. The Cut layer is the one which has the vias. Now let us learn how each layer is defined in LEF file:

      1. LAYER (cut) :
                    Cut layer consist of the 'via' connecting the metal layer above to the layer bellow. There are many attributes that are used to specify the cut layer rules. Let us see them in brief.

          ACCURRENTDENSITY - Specifies how much AC current the cut layer of certain area can handle
                                                      at a certain frequency.
          ANTENNAAREAFACTOR - This is some thing like a derate factor. The metel layers should adhere
                                                        to the antenna rules of the technology. In order to calculate the metal
                                                        area the actual metal area is multiplied with this area factor. To know in
                                                        detail about the antenna effect see process antenna effect.
          ANTENNAAREARATIO - Specifies the ratio of metal area to the diffusion area connected to the
                                                       metal node.
          ANTENNACUMAREARATIO - 


           

SED command line : Easy use guide

SED is a very powerful text processor which you can use to accomplish some tasks on the input file. As a vlsi engineer it is a must to have some basic knowledge about the sed language in order to execute your tasks efficiently. Remember efficiency only comes when it is done in fast and reliable manner.


The usage of sed is :

sed OPTIONS [script] [input file.....]

Some of the very useful commands are :

1. 's' for substitute :

example usage is : sed 's/day/night/' input_file >> output_file

The above command would replace 'day' with 'night' in the input file and saves a new file 'output_file' with the modifications.

VIM : Auto complete of words when typing

VIM is a very powerful text editor so far i have ever come across because no other text editor has such an extensive commands for editing text. Here is the one which would make you love vim for all its rich text editing commands.

Think of when you are writing an RTL code where you often use same names often in the file. Vim makes it easy for you in this scenario. It can auto complete your word by matching it with "previous", "next" matching words. We need to type few letters of the word and it is already used in the file then you can use the bellow commands to insert the same word without typing the word again.

Ctrl+n : insert the next matching word.

Ctrl+p : insert the previous matching word.

In the similar way, if you are trying to type a unix path in the file then you can type in directly without the knowledge of the absolute path by using

 Ctrl+xf : list the available dirs/files in the path.

VIM : Delete all the lines containing the pattern specified

VIM has a very useful command "g" which can be used to perform operations over the lines which contains the matched pattern.

The Syntax is :

:g/pattern/d

The above command deletes all the lines containing the pattern.

If you want to delete all the lines not containing the pattern then use the command as :

:g!/pattern/d

Note that the "g!" is equivalent to "v" hence the above command can also be performed using "v" as :

:v/pattern/d

You can match multiple pattern using "or" character "|" as bellow :

:v/pattern1\|pattern2\|pattern3/d

The above command deletes all the lines that does not contain the three patterns pattern1, pattern2 and pattern3.

ABOUT PLL (Phase Locked Loop)

       The Phase locked loop is a closed loop frequency control system based on the difference between the input clock signal and feedback clock signal from the VCO (Voltage Controlled Oscillator). Generally the PLL contains following components 

                    1. Phase and Frequency difference detector.

                    2. Voltage Controlled Oscillator.

                    3. Feedback Counter

                    4. Pre-scale Counter

                    5. Post-scale Counter

Phase and Frequency difference detector :

This circuit detects if the feedback clock signal is lagging or leading the input clock signal and generates an 'up' or 'down' signal. This Up or Down signal is used by the charge pump and VCO to align the phase and increase of decrease the output clock frequency.

The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.

The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.

When the reference clock and the feedback clock phases are aligned then the PLL is considered to be locked.

A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.

The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).

In the form of equations:

where:

• F_REF = F_IN / N

• F_VCO = F_REF × M = F_IN × M/N

• F_OUT = F_VCO / C = (F_REF × M) / C = (F_IN × M) / (N × C)

• F_VCO = VCO frequency

• F_IN = input frequency

• F_REF = reference frequency

• F_OUT = output frequency

• M = counter (multiplier), part of the clock feedback path

• N = counter (divider), part of the input clock reference path

• C = post-scale counter (divider)

Setup and Hold Basics

           Synchronous designs have become very popular because of their deterministic behavior. All the data need to satisfy MAX (Setup) and MIN (hold) delay constraints. All this is determined by the clock. Clock in a synchronous design can be thought of as a heart beat of the system. Figure bellow illustrates a simple data propagation between two memory stages.

                      In the above diagram, there are two D flip-flops having a combinational logic between them. Td is the delay due to the combinational logic. Lets mark the flops as A and B for our simplicity. The requirement of the synchronous design is that the clocks that are interacting should have a fixed phase and frequency relationship. Lets us assume that Ck1 and Ck2 is propagated from a common starting point to the two flops as shown above. The latency due to this clock propagation from the start point to the flop clock pin is called as Clock Latency. This can be simplified as shown in the figure bellow.

In the above diagram, Ck1 and Ck2 are the clock latency of Clk1 and Clk2 respectively. Clocks usually have start point from either one of the following, PLL outputs, Primary inputs, Clock divider logics etc. Taking, 

                                  Tper as clock period

                                  Td-slow as maximum combinational delay.

                                  Tsu- Setup time of the flip flop

                                  Thold - Hold time of the flip flop

                                  Td-fast - minimum combinational delay.

 we can arive at the equations of the setup and hold time requirements.

Setup Requirement :

The setup requirement says that the clock period of the clock must be always be greater than or equal to the sum of the data delay , setup time and difference in the clock latency of the two clocks.

Hold Requirement :

The hold requirement states that the minimum delay of the data should be always greater than or equal to the hold time requirement and the difference in the clock latency of the two clocks.

Why is these requirements ?
               These equations are what the implementation engineer and all the tools try to satisfy. But why is this  requirement exist. Ok lets jump into the internals of the flip flop. D flip flop is a master slave latch gated by clock.

Latches are very simple in operation. when the gate is on the output reflects the input. when the gate is closed the last value is latched. But why are they not used instead of flip flops ? Because this is not reliable because the input changes are

ABOUT ARM

     ARM architecture is a RISC (Reduced Instruction Set Computing) based computing processor architecture developed and licensed by ARM Holdings (Advanced RISC Machines).  

     Reduced Instruction Set is mostly mistaken for few or lesser number of instructions. In fact it actually intends that the amount of work accomplished in an instruction is reduced which is unlike the CSIC (Complex Instruction Set Computing)which involves many memory cycles and compute cycles per instruction.

     ARM addresses wide range of market segments and there by has  categories of its processors as shown in the figure.

      

 Cortex A : Is a class of application processors which can 

execute complex Operating Systems such as Android, linux/crome , Microsoft Windows. This class of processors integrates a Memory Management Unit (MMU) to manage the memory requirements of these complex OSs and enable the download and execution of third party software. Applications where they are used are

• Smartphones
• Feature Phones
• Tablets / eReaders
• Advanced Personal Media Players
• Digital Television
• Set-top Boxes & Satellite Receivers
• High-End Printers
• Personal Navigation Devices
• Server
• Enterprise

 Cortex R : Is an Embedded Real time processor which often execute Real Time Operating System (RTOS)alongside user-developed application code requiring only a Memory Protection Unit (MPU) as opposed to the MMU available in the Application Processors. Applications where they are used are

• Automotive Control Systems
• Wireless and Wired Sensor Networks
• Wireless base station infrastructure
• Mass Storage Controllers
• Printers
• Network Devices

 Cortex M : Embedded Processors can provide an optimum solution for very low-power embedded computing applications. Often provided as a “black box” with pre-loaded applications, they have limited capability to expand hardware functionality and in most cases no screen. Applications where they are used are

• Merchant MCUs
• Automotive Control Systems
• Motor Control Systems
• White Goods controllers
• Smart Meters
• Sensors
• Internet of Things

  

SecureCore : A number of SecurCore™ processors are available enabling Partners to choose the solution that fits the specific criteria of their application based on desired performance, die area, size, dynamic and static power, and other considerations.

SecurCore applications include:

• SIMs
• Smart Cards
• Advanced Payment Systems
• Electronic Passports
• Electronic Ticketing
• and Transportation

Interchange two columns in VIM

Sometimes we might be working on the databases where we require swapping of the columns. There may be many ways but what u found most interesting is this method.

1. First we need to provide the range over which the swapping need to be done. In this case the range is lines. If you want to swap the columns across all the lines in the file, then use % sign. % means all lines in the file.

2. Then we need to substitute the existing columns with the changed ordered column. For that we are going to use the substitute command 's'.

3. Then we need to provide the pattern to be matched. In this case the columns to be swapped need to be matched. In the same time we need to have them in the memory so that we can substitute them with the chaged order. For this we can make use of '\(' and '\)' before and after the patterns. This makes the vim to save them in the variable '1', '2'... etc upto '9'.

               \(pattern1\) \(pattern2\)
The space between the two patterns is the delimiter between the columns. It can be anything. I have used space here for the example. If you don't have a regular pattern to be matched then you can use '.*' to match the word like :
               \(.*\) \(.*\)

4. Then we need to specify the pattern to be replaced with. This is done using our saved variable. '1', '2' etc.
                   \1 \2

An example would be like this :

 :%s/\(.*\) \(.*\)/\2 \1/c

:                   command line prompt
%                 on all the lines
s                   substitute
\(.*\)             matches the first word (first column)
space -         matches the space after the name
\(.*\)            matches the second word (i.e, second column)
\2                 variable that holds the second matched word
\1                 variable that holds the first matched word
c                  substitute only on confirmation

'grep' command to match only the words in a text file

While i was doing my usual office work i got a situation where i need to get the list of words that match a pattern from a text file. After many google searches and man page reads i found the solution. Let this help someone else who gets into the same situation of mine.

grep : usually greps lines containing the pattern

-o : option specifying to match only the part of the line that matches the PATTERN

Example : 

grep -o PATTERN file_name

PATTERN here can be any regular expression also. Use -P for specifying perl regular expressions. 

Example : 

grep -o -P mr_.*_sad file_name

to match the words 

1. mr_harish_is_sad

2. mr_suresh_is_great